In many applications, a digital synthesizer is implemented by way of a digital phase locked loop (DPLL) that is used to control a digitally controlled oscillator (DCO) to generate (synthesize) an output frequency signal. Such digital synthesizers provide the benefit of simplifying the integration of the synthesizer circuity within large scale integrated digital circuit devices, as compared with equivalent analogue synthesizers, thereby reducing size, costs, power consumption and design complexity. Furthermore, DPLLs intrinsically present lower phase noise than their analogue counterparts.
In applications such as automotive radar systems, phase noise introduced into the output frequency signal by the synthesizer is critical. In the case of radar systems, the phase noise dictates the system's ability to distinguish between small and large targets (i.e. the dynamic range of the radar system). Accordingly, for such applications it is important to minimize the phase noise introduced by the digital synthesizers (e.g. DPLLs), and specifically their DCOs, as well as to linearize the FMCW (frequency modulated continuous wave) ramp in the case of a FMCW system.